Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems

摘要

This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. The approach was hierarchical, based on but Considerably expanding the practice used for Verification of the CMOS-based IBM S390 Parallel Enterprise Server~TM G4. For POWER4, Verification began at the abstract, high-level Design phase and continued throughout the Designer and unit levels, the multi-unit level, And finally the multiple-chip system level.