Preface

摘要

In future systems, continuing performance improvements, power efficiency, and smaller form factors for both portable product applications and fixed location products will be important. Take, for example, the billions of portable cell phones sold each year wherein the higher function products in this family seek increasing function with each generation while maintaining a fixed size. Another example is high-performance computing systems in which higher performance levels and high power efficiency are leading to high-bandwidth and low-latency multicore processors linked to ever higher stores of close proximity memory. Traditional planar system hardware architectures such as system-on-a-chip and system-in-package will no doubt continue to support most volume product electronic applications for decades into the future just as they have in the past. These technologies offer great product flexibility and leverage the worldwide manufacturing infrastructure that is in place today. However, even though future CMOS scaling will achieve higher transistor densities, the 50-60% system performance improvement per technology node, historically seen through the 90-nm node, will drop to under a 20% improvement per node beyond the 45-nm node if the system architectures remain planar.