Design and verification of DEFLATE acceleration as an architected instruction in z15

摘要

The IBM z15 processor chip contains a new hardware component to perform DEFLATE compliant compression and decompression. The Integrated Accelerator for zEnterprise Data Compression is based on a high-frequency DEFLATE pipeline and includes a hardware generator for dynamic Huffman tables. Accessible as an architected instruction, this engine has been designed for straight forward exploitation by software and is easily available to any application in the problem state. A brand-new hardware/firmware integration model has been developed to provide this complex functionality without imposing restrictions on data patterns or data sizes and without impacting system responsiveness. This article describes the concept, implementation, and verification of DEFLATE compliant compression acceleration in z15 across both hardware and firmware. It illustrates various challenges that result from incorporating complex data-dependent and data-intense functionality like DEFLATE as an architected instruction and discusses how solutions in hardware/firmware codesign have been applied to overcome these challenges.