Delay Regulation—A Circuit Solution to the Power/Performance Tradeoff

摘要

This paper introduces the concept of delay regulation as a means of controlling circuit delay variations from chip to chip, which is especially important in VLSI products. An embodiment of this concept which applies a phase-locked loop to individually control chip performance and power is presented together with computer-simulated results of an example design. It is shown that accurate delay equations and the potential for improved product yield result from application of the concept. The circuit overhead for large circuits is shown to be negligible. Application to a wide range of logic circuit types is also described.