机译:神经网络加速器概述
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;
School of Computer Science and Technology, University of Science and Technology of China, Hefei 230026, China;
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;
State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China;
neural networks; accelerators; FPGAs; ASICs; DianNao series;
机译:基于FPGA的卷积神经网络的加速器调查
机译:[DL]基于FPGA的神经网络推理加速器概述
机译:深度神经网络加速器体系结构概述
机译:基于图形卷积神经网络加速器的FPGA调查
机译:基于FPGA的嵌入式设备卷积神经网络的加速器
机译:采用离散时间细胞神经网络的181 GOPS AKAZE加速器用于实时特征提取
机译:基于任务的神经网络加速器在内存约束下的探索