A method is described for reducing operations that are not valid in processing layers of systems, integrated circuits, and neural networks. One or more tiles perform operations, each tile receives an input neuron, an offset, and a synapse, and each input neuron has an associated offset. Each tile produces an output neuron, and there is an activation memory that communicates with the tile via a dispatcher and encoder for storing the neuron. The dispatcher reads the neuron from the activation memory, communicates the neuron to the tile, reads the synapse from the memory, and conveys the synapse to the tile. The encoder receives output neurons from the tiles, encodes them and communicates the output neurons to the activation memory. The offset is processed by the tile to perform operations only on non-zero neurons. Optionally, synapses can be similarly processed to skip operations that are not valid. [Selection] Figure 5B
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