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Constructive Boolean circuits and the exactness of timed ternary simulation

机译:构造布尔电路和定时三元模拟的准确性

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We classify gate level circuits with cycles based on their stabilization behavior. We define a formal class of combinational circuits, the constructive circuits, for which signals settle to a unique value in bounded time, for any input, under a simple conservative delay model, called the up-bounded non-inertial (UN) delay. Since circuits with combinational cycles can exhibit asynchronous behavior, such as non-determinism or metastability, it is crucial to ground their analysis in a formal delay model, which previous work in this area did not do. We prove that ternary simulation, such as the practical algorithm proposed by Malik, decides the class of constructive circuits. We prove that three-valued algebra is able to maintain correct and exact stabilization information under the UN-delay model, and thus provides an adequate electrical interpretation of Malik's algorithm, which has been missing in the literature. Previous work on combinational circuits used the upbounded inertial (UI) delay to justify ternary simulation. We show that the match is not exact and that stabilization under the Ul-model, in general, cannot be decided by ternary simulation. We argue for the superiority of the UN-model for reasons of complexity, compositionality and electrical adequacy. The UN-model, in contrast to the Ul-model, is consistent with the hypothesis that physical mechanisms cannot implement non-deterministic choice in bounded time. As the corner-stone of our main results we introduce UN-Logic, an axiomatic specification language for UN-delay circuits that mediates between the real-time behavior and its abstract simulation in the ternary domain. We present a symbolic simulation calculus for circuit theories expressed in UN-logic and prove it sound and complete for the UN-model. This provides, for the first time, a correctness and exactness result for the timing analysis of cyclic circuits. Our algorithm is a timed extension of Malik's pure ternary algorithm and closely related to the timed algorithm proposed by Riedel and Bruck, which however was not formally linked with real-time execution models.
机译:我们根据周期的稳定行为对门级电路进行分类。我们定义了形式化的组合电路类别,即构造电路,在简单的保守延迟模型(称为上界非惯性(UN)延迟)下,对于任何输入,信号在有界时间内都稳定为唯一值。由于具有组合周期的电路可能表现出异步行为,例如不确定性或亚稳定性,因此至关重要的是将它们的分析基于正式的延迟模型,而这在该领域以前是无法做到的。我们证明三元仿真(例如Malik提出的实用算法)决定了构造电路的类别。我们证明了三值代数能够在UN延迟模型下保持正确和精确的稳定信息,从而为Malik算法提供了充分的电学解释,而文献中一直没有这种解释。先前在组合电路上的工作使用上惯性(UI)延迟来证明三元仿真的合理性。我们表明匹配并不精确,并且在Ul模型下的稳定性通常无法通过三元模拟确定。我们出于复杂性,组成性和电力充足性的原因而主张联合国模式的优越性。与Ul模型相反,UN模型与物理机制无法在有限时间内实现非确定性选择的假设相一致。作为主要结果的基石,我们介绍了UN-Logic,这是一种用于UN延迟电路的公理规范语言,它在实时行为及其在三进制域中的抽象仿真之间进行中介。我们针对以联合国逻辑表达的电路理论提出了一种符号模拟演算,并证明其对于联合国模型是合理且完整的。这首次为循环电路的时序分析提供了正确性和准确性。我们的算法是Malik纯三元算法的定时扩展,与Riedel和Bruck提出的定时算法密切相关,但是该算法并未与实时执行模型正式关联。

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