As many test professionals have been aware and as more became aware after Pat Gelsinger's often-quoted ITC 1999 keynote address, cost of test is the issue. Test-vector compression is only one means of reducing test cost, and there are a number of schemes vying for market share, especially now that cost of test has become the industry's dominant concern. You need to understand the differences among the approaches to make an informed choice. Whether viewed as a means of compressing ATPG vectors or as a way to make BIST structures have better fault coverage, vendors of most compression approaches promise similar benefits. The initial choice is between a true BIST solution and one of the test-vector compaction methods, followed by selection of the product that best matches your needs. Realistically, however, few designers or test engineers have had a truly free choice in this matter. Because test-circuit insertion and test-vector generation are intimate parts of the design flow, the only practical solution for most companies has been to use the test tools that complemented the electronic design automation (EDA) tools they already had in place. As more EDA products join the trend toward standards-based open architectures using the standard test interface language (STIL) and its extensions, mixing tools from different vendors should become a viable option.
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