A hardware processor for implementing the pyramid vector quantizer

摘要

A single-chip, dedicated processor for implementation of pyramid vector quantization (PVQ) is presented. The computational requirements of the vector quantizer encoding the algorithm are described, and a processor architecture and instruction set are selected for efficient implementation of the vector quantization. The architecture's performance was simulated at the register transfer level with the Lisp language, and Monte Carlo estimates of processor execution times are presented. A Texas Instrument's TM32020-based PVQ implementation is also examined and compared to the proposed PVQ processor. It is found that for a state-of-the-art VLSI implementation, 64-dimensional vectors can be vector quantized at an arbitrary encoding rate and at sampling frequencies of up to 16 kHz.