Presents and discusses an improved performance token ring network interface adapter. The description includes that of the adapter architecture, the internal serial bus structure, and the dual latency data path bypass circuitry. It is shown that these enhancements lead to improvements in the performance measures of interest for real-time applications. Critical portions of the circuit were fabricated using a laser direct-write gate array metallisation system. The interface adapter performance results, based on both logic simulation results and timing measurements made on the fabricated chips, are also described. Network performance results are presented, based on a network simulation incorporating the characteristics of the improved network interface adapter. The reported results show a significant performance improvement, specifically, a reduction in mean message waiting time, which is particularly important for applications of token ring networks requiring time-critical performance.
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