Modelling and analysis of bridging faults in emitter-coupled logic (ECL) circuits

摘要

With the recent achievement of lower power and higher densities, bipolar ECL technology is expected to be used widely in high performance digital circuits. Recent investigations have revealed that bridging faults can be a major failure mode in ICs. The paper presents a detailed analysis of bridging faults in ECL. Certain bridging faults manifest as stuck-at faults. Effects of bridging faults between logical units without feedback and logical units with feedback in ECL are presented. An analytical approach is presented for computation of logic levels at ECL outputs under varying unknown bridging resistances. Effects of bridging faults and bridging resistances on output logic levels in ECL have been examined along with their effects on noise immunity.