Estimating power consumption of CMOS circuits modelled as symbolic neural networks

摘要

The authors propose a new approach to the problem of estimating the average power consumption of a CMOS combinational circuit which is based on neural models. Given the gate level description of a circuit, they build the corresponding Hopfield neural network, store it, calculate the energy dissipated by the network and, finally, derive the power dissipated by the original circuit. All the operations above are executed in the symbolic domain, that is algebraic decision diagrams are used to represent and manipulate the graph specification of the neural network modelling the circuit. The approach is viable and computationally efficient. In addition, it produces power estimates which are, on average, as accurate as the ones computed by state-of-the-art power analysis tools.