Studying the effects of mismatching and clock-feedthrough in switched-current filters using behavioral simulation

摘要

Mismatching and clock-feedthrough are sources of error in Switched-Current (SI) circuits producing DC offset, gain errors, and harmonic distortion, which cause deviations in SI filter responses in both the passband and the stopband. This paper develops formulas including these effects in the input-output description of filter building blocks to make possible not only a faster prediction of the filter performance levels but also to analyze tradeoffs at the early design stages. The block input-output descriptions have been derived taking into account the real physical realization of these blocks together with simple error models. Using these behavioral input-output descriptions, we have studied the extent of these effects in the performance of two different SI filter realizations of passive LC ladder structures: one using integrators to simulate the signal flow graph (SFG) of the ladder and another based on the use of wave active filter (WAF) structures. Monte Carlo simulations of a filter example are presented and analyzed.