HDL-specific source level behavioural optimisation

摘要

Optimisation is a key facet of the behavioural synthesis problem. The process may be carried out at different levels in the processing, usually at the source or datapath levels, or both. In a previous paper, the authors reported a source level VHDL optimiser which applies optimisation techniques derived from conventional sequential and parallel programming languages. This process produces structural descriptions that are up to 33% faster and 20% smaller than the corresponding 'brute force' mapping of behaviour to structure. In the paper the authors describe a further set of optimisation transforms that may be applied at the source level to a VHDL behavioural description. These transforms have no conventional programming language counterpart, and are specific to hardware description languages. A number of designs have been optimised with respect to area and/or delay, with and without these transforms. The results show that with this extra class of transforms there is an improvement of /spl sim/44% in delay and 38%, in area.