Bandpass /spl Sigma//spl Delta/ modulator employing undersampling of RF signals for wireless communication

摘要

The rapid development of digital wireless systems has led to a need for high-resolution and high-speed bandpass analog-to-digital converters. Continuous-time bandpass /spl Sigma//spl Delta/ modulators are very suitable for such high frequency applications. In this paper, analysis and simulation of a continuous-time bandpass /spl Sigma//spl Delta/ modulator for use in modern cellular/PCS receivers is given. The design employs undersampling relative to a radio receiver's radio frequency (RF) or intermediate frequency (IF) center frequency, while oversampling the signal bandwidth. This technique enables clocking at a frequency much lower than the RF/IF frequency, allowing use of standard CMOS technology and reducing the complexity and power consumption of subsequent digital signal processing stages. The analysis shows that it is possible to achieve a loop transfer function that matches a standard discrete-time bandpass /spl Sigma//spl Delta/ modulator while operating at sample rates significantly lower than conventional bandpass architectures.