首页> 外文期刊>Emerging and Selected Topics in Power Electronics, IEEE Journal of >Behavioral Device-Level Modeling of Modular Multilevel Converters in Real Time for Variable-Speed Drive Applications
【24h】

Behavioral Device-Level Modeling of Modular Multilevel Converters in Real Time for Variable-Speed Drive Applications

机译:变速驱动应用中的模块化多电平转换器的行为设备级实时建模

获取原文
获取原文并翻译 | 示例
           

摘要

This paper presents the real-time hardware-in-the-loop (HIL) emulation of an induction machine (IM) driven by a modular multilevel converter (MMC) on the field-programmable gate array (FPGA). The insulated gate bipolar transistors and antiparallel diodes of the MMC are modeled with nonlinear static and dynamic characteristics to provide not only accurate system-level performance of the converter but also insight into the power losses under different operation conditions. Due to the large network size of the MMC, its solution in conjunction with the IM fifth-order model proved to be a significant computational challenge. Therefore, circuit partitioning based on the transmission line modeling is proposed, which introduced an interface to the electrical network for the IM as well as split the multiloop MMC into several smaller subcircuits in terms of matrix size, and consequently enabled a fully parallel implementation on the FPGA. Control strategies for the MMC and IM are also emulated in hardware, and due to the large latency difference between subcircuits and controllers, the overall system hardware design is divided into several layers, each having an independent time step ranging from 500 ns to so as to attain the goal of real-time execution. A comparison of transient and steady-state results from the HIL emulation and offline simulation tools shows high accuracy of the modeling approach as well as the efficacy of proposed multiple time steps in achieving real time.
机译:本文介绍了由现场可编程门阵列(FPGA)上的模块化多电平转换器(MMC)驱动的感应机(IM)的实时硬件在环(HIL)仿真。 MMC的绝缘栅双极型晶体管和反并联二极管采用非线性静态和动态特性建模,不仅可以提供转换器的精确系统级性能,还可以洞察不同工作条件下的功耗。由于MMC的网络规模较大,因此将其解决方案与IM五阶模型结合起来证明是一项重大的计算挑战。因此,提出了一种基于传输线建模的电路划分方法,该方法为IM引入了一个电气接口,并根据矩阵大小将多环MMC分成了几个较小的子电路,从而实现了对MIM的完全并行实现。 FPGA。 MMC和IM的控制策略也可以在硬件中进行仿真,并且由于子电路和控制器之间的巨大延迟差异,整个系统硬件设计被分为几层,每层具有独立的时间步长,范围从500 ns至达到实时执行的目标。从HIL仿真和离线仿真工具获得的瞬态和稳态结果的比较表明,该建模方法具有很高的准确性,并且建议的多个时间步长可以实现实时性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号