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A Complementary Resistive Switch-Based Crossbar Array Adder

机译:基于互补电阻开关的交叉开关阵列加法器

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Redox-based resistive switching devices (ReRAM) are an emerging class of nonvolatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic “sneak” currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti
机译:基于氧化还原的电阻式开关设备(ReRAM)是一类新兴的非易失性存储元件,适用于纳米级存储器应用。在逻辑运算方面,建议将ReRAM器件用作可编程互连,大规模查找表或用于顺序逻辑运算。但是,如果没有其他选择器设备,这些方法将不适合用于大规模的纳米交叉开关存储阵列,由于其最小的面积消耗,这是ReRAM设备的首选架构。为了解决顺序逻辑方法的这一问题,我们最近引入了一个新颖的概念,该概念适用于使用互补电阻开关(CRS)的无源交叉开关阵列。 CRS单元提供两种高电阻存储状态,因此,可以有效避免寄生“潜电流”。但是,直到现在,基于CRS的内存中逻辑方法仅显示为能够使用单个CRS单元执行基本的布尔逻辑运算。在本文中,我们使用基于CRS的内存中逻辑方法介绍两种多位加法器方案。我们使用ReRAM单元的动态忆阻器件模型通过SPICE仿真来验证概念。最后,与最近发布的加法器方法相比,我们展示了新颖的加法器概念在步数和器件数量方面的优势,后者采用了Borghetti提出的基于ReRAM的常规顺序逻辑概念

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