FIT-FAST STRUCTURED ARRAYS UNLEASH CUSTOM-IC PERFORMANCE AT FPGA VOLUMES

摘要

A new architecture featuring standard cells configured using a small number of metal layers significantly shortens development time and reduces NRE costs allowing low-volume projects to benefit from ASIC-like performance and power consumption. Designers targeting a custom IC must typically choose between implementing their design in either an FPGA or standard-cell ASIC. An FPGA is usually the most economical solution if the intended production volume is low, since up-front costs are very low although the per-unit cost is relatively high compared to an ASIC. The overall cost for an ASIC is calculated by a combination of the per-unit cost, which is much lower than the FPGA case, and also Non-Recurring Engineering (NRE) costs such as the costs of masks, package design and test development. The impact of the longer lead-time for an ASIC solution, in terms of potential opportunity costs, should also be considered. On the other hand, implementing a given design in an ASIC can result in higher performance and lower power consumption compared to an FPGA.