Low-noise wideband PLL with dual-mode ring-VCO

摘要

A low-jitter 110 MHz-to-620 MHz phase-locked loop (PLL) that includes a low-noise widc-frequency-range ring oscillator with a dual-mode operation is presented. The measurement results using a 65 nm low-power CMOS process show that the proposed PLL achieves as low as a 2.5 ps RMS jitter at 600 MHz of output frequency while consuming 2.7 mW at a 1.2 V supply. The die area is only 0.09 mm~2.