2.56 GHz sub-harmonically injection-locked PLL with cascaded DLL for multi-phase injection

摘要

A 2.56 GHz injection-locked phase-locked loop (ILPLL) cascaded with a delay-locked loop (DLL) for minimising phase noise is presented. Generally, an ILPLL includes an injection-locked voltage-controlled oscillator (ILVCO), which is directly injected with the reference clock phase. However, the proposed scheme connects the output multi-phased clocks of the DLL to the injection node and they can be selected with turn on/off switches. This can shorten the realignment time of the VCO phases and thus the in-band phase noise is decreased. The proposed circuit is implemented in a 65 nm CMOS technology, and reduces the phase noise by 10.86 dBc/Hz at a 1 MHz offset with 16 multi-phased injections, compared with a conventional PLL.