Lattice's latest 3.3 volt family - the 5000V family of Superwide CPLD's are E~2 CMOS technology based. They provide the design engineer with an extremely wide fan-in to accommodate the latest bus widths of 32 & 64 bits. Deserving the "W" - for Widest - in Lattice's BFW CPLD strategy, the 5000V family devices are ideal for interfacing to DSP datacornm applications. The new family provides the following features: 1. SuperWide Programmable Logic Blocks - 32 Macrocells per GLB 2. 3.3V Power Supply 3. 12500 to 25000 PLD Gates/25 to 512 Macrocells 4. 7.5-ns/125-MHz performance 5. 3.3V/2.5V User Selectable Outputs 6. JTAG Boundary Scan Test 7. 208-492 Leads in BGA Packages.
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