Chip-to-Module Interconnections

摘要

Future integrated circuit (IC) packaging requirements and the performance of chip-to-module interconnections are determined by the expected chip performance. For example, the International Technology Roadmap for Semiconductors~1 specifies that high-performance chips at the 70 nm technology node will cover an area of 427 mm~2, have 4437 input/output (I/O) pins, operate with an on-chip local clock speed of 6 GHz and have a chip-to-board speed of 2.6 GHz. These same chips will dissipate overl71Wof power and draw 190 A of dc current. At the 35 nm technology node, high-performance chips will require interconnections that can support 8758 pins and operate at 16.9 GHz (on-chip) and 3.8 GHz (off-chip). They will dissipate 186 W of heat and consume 310 A dc current.