Integration of a RISC processor core into a disk controller ASIC

摘要

The design experience in core integration is described here with a current ASIC project where the work task was the integration of a processor core into a disk controller chip. The processor core from ARM is a 32bit RISC processor with a 16bit mode. This core is not comprised of RTL synthesizable HDL, but instead exists as a hard library macro, with behavioural models provided by ARM and the physical layout and timings generated by GEC Plessey Semiconductor, the ASIC foundry.