Manufacturing, test to designers: We need to talk: Big problems looming at 65 nm demand bolder strategies

摘要

San Francisco - Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at last week's Semicon West show here: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation. Designers may need to rely heavily on more expensive phase-shift masks and other enhancement techniques, at least until a somewhat delayed 157-nm lithography solution arrives. Similarly, problems with porous low-dielectric-constant (low-k) materials may force chip designers to add repeaters to global interconnects. At the same time, speakers and panelists said, challenges in bringing on a high-k gate insulator could bedevil designers worried about current leakage and reliability.