Vectorless test: best bet for high-speed I/O

摘要

High-volume manufacturers must wrestle with the conundrum of how to cost-effectively test multiple multilane high-speed I/O interfaces―such as PCI Express, Hyper-Transport and Infini-band―embedded into huge digital system-on-chip designs. While on-chip built-in self-test (BIST) combined with a loopback operation is a widely adopted alternative to costly automatic test equipment (ATE), it suffers from poor fault coverage of the high-speed analog portion, significantly affecting overall product quality. Now, an approach called vec-torless test is emerging that offers the best of both approaches: the cost-effectiveness of on-chip I/O BIST combined with ATE-based signal integrity measurements. Specifically, the concept unites ATE parametric testing with on-chip test content generation and compare, forming a synergy between silicon and ATE. The result is an economical optimized solution for high-volume manufactruing test designed into the silicon, using established electronic-design-automation techniques.