The IEEE is pushing ahead to make Verisity Ltd.'s proprietary "e" an industry-standard verification language and to define the next revision of Verilog. But an apparent rift with the Accellera standards organization has raised the risk that Accellera's SystemVerilog 3.1 may diverge from the standard eventually approved by IEEE. The standards jockeying will serve as a dramatic backdrop here this week as the 40th Design Automation Conference convenes. Verisity will announce this week that the IEEE Design Automation Standards Committee (DASC) has approved a project authorization request (PAR), named IEEE 1647, to develop a standard verification language based on "e." That's good news for the thousands of customers who have legacy "e" code. But some engineers question whether there will be a future need for "e," given that SystemVerilog 3.1 adds assertions and testbench constructs.
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