Virtual Silicon takes new path to power savings

摘要

San Mateo, Calif. ― The problem of subthreshold leakage current in advanced CMOS processes is attracting attention as more design teams undertake low-power designs at 130 nm or below. Electrically, the problem is simple: To make the tiny transistors in these geometries fast at the tiny operating voltages they can tolerate, their threshold voltage must be very low. But the lower a MOS transistor's threshold voltage, the larger the source-drain current that flows when the transistor is nominally off. At 180 nm, that was an interesting second-order issue. But at the lower threshold voltages used in 130 nm, subthreshold leakage can contribute a noticeable fraction of a chip's total power consumption.