Fremont, Calif. —Tensilica Inc. has long made the argument that a small, efficient RISC core with instruction extensions— generated automatically along with its testbench—can be a viable alternative to custom hardware development. The argument has rested on the idea that one can write out an algorithm in C, separate it into the noncritical 90 percent and the critical 10 percent, and then accelerate those critical inner loops with custom instructions. The overall gain in application throughput, often one or one and a half orders of magnitude, comes close to what could be achieved with a nonprogrammable data path, while keeping the application in software. Inherent in this argument was the idea that the really heavy lifting would be done by specialized hardware generated to accelerate the inner loops. The rest of the code would run on a not-particularly-blazing, vanilla RISC engine.
展开▼
