EDA startup looks to verify verification

摘要

Aromas, Calif. — In 2003, a trio of chip designers came up with a new idea for improving the quality of IC verification. This week their concept will see the light of day as Certess Inc., the venture-funded startup they launched to develop their "functional qualification" technology, announces itself. Functional qualification is basically a way of verifying the IC verification process itself. It promises to go far beyond today's code- and functional-coverage metrics, and tell verification engineers whether or not bugs in the design may be undetected. Certess (Campbell, Calif.) isn't announcing a product yet, but claims its technology is already in production use with three customers.