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Formal Methodology Validates Cache-Coherence Protocol

机译:正式方法论验证高速缓存一致性协议

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摘要

Uncovering architectural problems early can prevent costly redesigns downstream. For example, it's not feasible to achieve sufficient coverage at the design level for cache-coherence protocol checking. That's because there's too much sequential depth. To verify a cache-coherence protocol, a tool must consider a range of traces that are both wide (in terms of starting and branching points) and deep (with long sequences of events).
机译:尽早发现架构问题可以防止下游进行昂贵的重新设计。例如,在设计级别实现足够的覆盖范围以进行缓存一致性协议检查是不可行的。那是因为顺序的深度太多了。为了验证高速缓存一致性协议,工具必须考虑一系列迹线,这些迹线既宽(就起点和分支点而言)又较深(事件序列较长)。

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  • 来源
    《Electronic Design》 |2009年第15期|p.40-43|共4页
  • 作者单位

    scott meeth | SUN MICROSYSTEMS Scott.Meeth@sun.comNORRIS IP | JASPER DESIGN AUTOMATION ip@jasper-da.comHOLLY STUMP | JASPER DESIGN AUTOMATION holly@jasper-da.comed online 21476Scot Meeth, design/architecture formal verification engineer at Sun, received a BA in mathematics and a BS in computer science from the University of Florida, Gainesville, and an MS in mathematics and an MA in computer science from the University of Illinois at Champaign-Urbana.Noris Ip, director of engineering at Jasper Design Automation, received a PhD in computer science from Stanford University, Calif., and a master's/bachelor's degree in computer science from the University of Oxford, United Kingdom.Holly Stump, vice president of marketing at Jasper Design, received a BSEE from the Illinois Institute of Technology, Chicago.;

  • 收录信息 美国《工程索引》(EI);
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  • 正文语种 eng
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