A low-resistance self-aligned T-shaped gate for high-performance sub-0.1-/spl mu/m CMOS

摘要

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-/spl mu/m region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 /spl mu/m to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 /spl mu/m. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-/spl mu/m gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability.