Noise Margin Modeling for Zero- Load TFT Circuits and Yield Estimation

摘要

The flexible electronics is promising in the area of the Internet of Things and wearable devices and the thin-film transistor (TFT) technologies are crucial for flexible electronics. Among them, the zero- load TFT circuits are widely used for its simple structure and high gain merits. However, the yield model is lacking for zero- load TFT circuits. In this paper, the analytical noise margin model for the zero- load TFT NAND gate and NOR gate is derived. Based on that, a simple, accurate, and highly scalable yield model for the combinational TFT logic circuits based on standard cell library is further proposed. ISCAS’85 benchmark circuits are used to validate the yield model. Compared with Monte Carlo simulation, the model achieves 3–4 orders of magnitude speedup with comparative results.