SI-Aware Vias and Contact Pads Layouts and L--R Equalization Technique for 12 Gb/s Backplane Serial I/O Interconnections

摘要

With increasing demand on higher performance for high-speed blade servers, the signal integrity aware (SI-aware) layouts and equalization have been attributed as the critical techniques to improve the electrical performance. This paper describes the SI-aware layouts of patterned ground and capsule-shaped antipad to enhance the connector performance. Besides, a new differential equalizer by taking advantage of differential via-stubs is proposed to restore the deteriorated eye diagram. Their application of a 117.5-cm SATA-II links demonstrates significant improvement in eye height and timing jitter. Furthermore, a viable approach is suggested to successfully reopen the eyes when the data rate increases from the current 3 to 12 Gb/s. The measurement results are also provided to validate the proposed design concepts.