Parasitic inductance of a bypass capacitor

摘要

You can estimate the parasitic series inductance of a bypass capacitor in a multilayer board with solid power and ground planes. Use an approximation for the inductance L_1 due to the chip layout (Figure 1, green shaded region). Then, assuming that you have connected your chip and your bypass capacitor straight to the planes, use an approximation for the inductance L_2 represented by the volume of magnetic flux trapped between the planes (blue region). Finally, you might want to consider the inductance, L_3, of the chip package itself (red region). The internal details of the construction of a monolithic ceramic capacitor add little to the total inductance.