Simple design enhancements enable in-system test: part one

摘要

Any college freshman who has taken Economics 101 can summarize the subject in two words: supply and demand. Likewise, you can summarize testability in two words: observability and controllability. The testability techniques that most ASIC designers bring to bear on their designs are limited to internal scan and JTAG boundary scan, whose benefits lie almost exclusively in chip-and board-manufacturing test. (JTAG stands for Joint Test Action Group, which originally promulgated the standard that has since become IEEE 1149.1.) Several techniques exploit and extend internal scan and boundary scan to provide new ways of observing and, in some cases, controlling ASICs' internal logic to assist in testing and debugging devices and systems in the lab and even in the field.