Managing phase rotation in PLL synthesizers

摘要

Many RF systems, especially those related to the telecom market, need reference signals with accurate and stable frequencies. Singlechip PLLs (phase lock loops), such as those that several IC suppliers provide, have a standard architecture (Reference 1 and Figure 1). In the charge pump PLL, the output of the phase detector is a current pulse of fixed amplitude and of a duration equal to the phase difference between its two input signals. After the initial transient, these two signals reach the same frequency, f{sub}(COMPARE) and, ideally, the output of the phase detector neither sources nor sinks any current and appears as an infinitely large impedance.