SOC ASICs: overcoming verification and validation and validation challenges

摘要

WITH ANY SEMICONDUCTOR DEVICE, presilicon design verification and postsilicon validation are critical to the functional and operational quality of the finished product. This situation holds especially true for SOC (system-on-chip) devices, in which a single defect in any one function could cause the failure of the entire ASIC and necessitate a re-spin. At the same time, the integration of more functions into single devices, shrinking product-design cycles, and compressed verification and validation cycles because of time-to-market pressures are increasing device complexity. Platform offerings that include validated onboard chip-set components, such as IOPs (I/O processors), place additional timing pressure on verification and validation teams.