Have you ever seen a glitch such as the one at Gate A in Figure 1? This nonmonotonic glitch appears symmetrically in both rising and falling edges, although that scenario is not always the case. Can you guess what causes it? If you have a simulator handy, here's some data for your calculations. The clock-distribution network in Figure 1 operates at 200 MHz. The 50Ω driver generates symmetrical 400-psec rise and fall times.
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