Engineers have for many years used wide parallel dig- ital buses, such as PCI, SCSI, and parallel ATA, for interconnects in the computer and datacom industry. Over time, the clock speeds of these buses increased to several hundred megahertz. Although the pace may have slowed a little bit, the ever- increasing demand for more bandwidth naturally has led to ever-higher processor clock speeds. At clock rates of approximately 1 GHz, however, parallel buses have become roadblocks on the data highway. Currently, engineers could overcome these challenges, such as synchronizing parallel data lanes at rates greater than 1 GHz, only with massive, probably unjustified technical effort. This scenario is especially true if you consider that, all of a sudden, digital designers are in the realm of "digital microwave." Thus, they are often unprepared to cope with nasty effects, such'as EMI and jitter (phase noise). Traditionally, such effects occur only in RF designs, and engineers could ignore them at lower data rates.
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