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Testing gigabit serial buses: First, get physical

机译:测试千兆串行总线:首先,进行物理测试

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Because of fundamentally analog SI (signal-integrity) issues that accompany today's higher data rates, digital electronics is now as much analog as it is digital. As SI expert Eric Bogatin, PhD, chief technology officer of GigaTest Laboratories put it several years ago, "There are only two kinds of EEs: those who have had SI problems and those who will." Still, although you mustn't become complacent, system architects, IC gurus, and test-instrument designers are hard at work making digital design's transition to SI's ana-log world as painless as possible. Even so, most EEs will experience some discomfort. According to the classical view, the days when you could ignore SI ended when bus-clock rates passed approximately 50 MHz. At that point, give or take a few megahertz, when you designed buses or interconnects, you had to start taking terminations seriously and stop thinking of reflections as just a little overshoot and ringing on waveform edges at state changes. Today, clock rates have leapt upward by an additional factor of at least 50 to 2.5 GHz or more (equivalent to clock periods of 400 ps or less). At such speeds, terminations and reflections are only two of the SI issues on a long list that you must grapple with.
机译:由于当今更高的数据速率伴随着基本的模拟SI(信号完整性)问题,因此数字电子产品现在与模拟数字一样多。正如SI专家GigaTest Laboratories首席技术官Eric Bogatin博士几年前所说,“只有两种EE:有SI问题的人和有意愿的人。”尽管如此,尽管您不必沾沾自喜,但系统设计师,IC专家和测试仪器设计师仍在努力工作,以使数字设计向SI模拟世界的过渡尽可能轻松。即使这样,大多数电子工程师仍会感到不适。按照经典观点,当总线时钟速率超过大约50 MHz时,可以忽略SI的日子就结束了。到那时,给定或几兆赫兹的频率,在设计总线或互连时,您必须开始认真对待端接,并不再考虑反射,因为在状态变化时,波形会出现少许过冲和振铃。如今,时钟速率已经以至少50到2.5 GHz或更高的频率(相当于400 ps或更低的时钟周期)上升了至少两倍。以这种速度,终止和反射只是一长串您必须努力解决的SI问题中的两个。

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