DESIGNS THAT INCORPORATE backplanes and interconnects operating at greater than 1 Gbps require accurate Spice and IBIS (I/O-buffer-in-formation) models. At such speeds, these interconnects appear to be complex, often distributed structures that require careful design techniques; thus, signal integrity becomes a key factor in achieving reliable performance. This region magnifies issues such as frequency-dependent transmission and reflection losses, crosstalk coupling, and signal dispersion, especially when the interconnect structure is electrically long. Designers need to address the modeling challenges of the backplane structure to achieve a reliable digital-system design and simulation.
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