DIFFERENTIAL SKEW HAS BECOME A PERFORMANCE-LIMITING PHENOMENON. YOU CAN MANAGE IT WITH A VARIETY OF APPROACHES. Until recently, wide synchronous buses were the method of choice for high-data-rate digital communications because digital logic could not support the switching rates for required bandwidth on a single lane. Unfortunately, wide synchronous buses become problematical at high clock rates. As speeds increase and buses become wider, it becomes increasingly difficult to obtain required setup-and-hold times on all the lines in a wide bus. These facts have driven the use of very-high-bit-rate serial buses with embedded clocks. Embedded clocks are implicit in serial buses, and the clock frequency is 1/UI (unit interval) of data change. This article assumes an 80-psec UI and, therefore, a 12.5-GHZ clock frequency (Figure 1).
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