Pcell and IP realities for fabless design

摘要

The current methodology for SOC (system-on-chip) design employs a hierarchical approach that maximizes the use of IP (intellectual-property) blocks. This method replaces the previous one, which used flat files full of gate-level structures. Third-party IP providers and in-house groups supply these IP blocks. Most of the in-house-created IP blocks are hierarchical assemblages of primitive devices that automatic cell generators, such as Pcells, create.