New challenges for digital control of power converters

摘要

Advancements in semiconductor technologies and system-level performance requirements, particularly in the telecom and datacom markets, have had a tremendous impact on the board-level power infrastructure. Moore's Law has been driving device densities, with the consequential effects of driving frequencies higher and voltages lower. With as many as 20 different voltage rails on a single board, as low as 0.5 V and still falling, and with load currents exceeding 100 A, power has become a major challenge for the system architect. With the lower voltage requirements for today's electronics, one might also project a reduction in the power levels. In fact, we have witnessed just the opposite. In the 90s, power density per line card board was about 300 W and is on track to reach 3 kW by 2015 and 5 kW by 2020. But innovations beyond semiconductor geometries are also driving demands on power performance beyond the scope of increasing density and falling voltages. Multi-rail ASICs with voltage tracking and/or sequencing requirements along with total voltage regulation limits of ±1 percent include ripple and noise, transient deviations, and temperature effects. Operational transitions place intense demands on current slew rates. The employments of frequency scaling and dynamic core voltage adjustment are now commonly used to manage the total power dissipation.