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首页> 外文期刊>LIPIcs : Leibniz International Proceedings in Informatics >Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems
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Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems

机译:辨别性连贯性:数据共享多核实时系统中的平衡性能和延迟界限

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摘要

Tasks in modern multi-core real-time systems share data and communicate among each other. Nonetheless, the majority of published research in real-time systems either assumes that tasks do not share data or prohibits data sharing by design. Only recently, some works investigated solutions to address this limitation and enable data sharing; however, we find these works to suffer from severe limitations. In particular, approaches that bypass private caches to avoid coherence interference altogether suffer from significant average-case performance degradation. On the other hand, proposed predictable cache coherence protocols increase the worst-case memory latency (WCL) quadratically due to coherence interference. In this paper, by carefully analyzing the scenarios that lead to high coherence interference, we make the following observation. A protocol that distinguishes between non-modifying (read) and modifying (write) memory accesses is key towards reducing the effects of coherence interference on WCL. Accordingly, we propose DISCO, a discriminative coherence solution that capitalizes on this observation to balance average-case performance and WCL. This is achieved by disallowing modified data in private caches, and hence, the significant coherence delays resulting from them are avoided. In addition, DISCO achieves high average performance by allowing tasks to simultaneously read shared data in the private caches. Moreover, if the system supports the distinction between private and shared data, DISCO further improves average performance by allowing for the caching of private data in cores' private caches regardless of whether it is modified or not. Our evaluation shows that DISCO achieves 7.2?- lower latency bounds compared to the state-of-the-art predictable coherence protocol. DISCO also achieves up to 11.4?- (5.3?- on average) better performance than private cache bypassing for the SPLASH-3 benchmarks.
机译:现代多核实时系统中的任务共享数据并相互通信。尽管如此,实时系统中的大多数已发表的研究要么假定任务不共享数据或禁止通过设计共享数据。只有最近,一些作品调查了解决方案,以解决此限制并启用数据共享;但是,我们发现这些作品遭受严重的局限性。特别是,旁路私人高速缓存以避免相干干扰的方法遭受显着平均例子性能下降。另一方面,所提出的可预测的高速缓存相干协议由于干扰而二次增加最坏情况的内存延迟(WCL)。在本文中,通过仔细分析导致高相干干扰的情景,我们进行以下观察。在非修改(读取)和修改(写入)存储器访问之间区分的协议是降低WCL对一致性干扰效果的关键。因此,我们提出了迪斯科舞会,一种辨别性的一致性解决方案,可以利用这种观察来平衡平均案例性能和WCL。这是通过禁止私人高速缓存中的修改数据来实现的,因此避免了由它们产生的显着的相干延迟。此外,迪斯科舞厅通过允许任务在私人高速缓存中同时读取共享数据来实现高的平均性能。此外,如果系统支持私有和共享数据之间的区别,则迪斯科芯可以通过允许在核心高速缓存中缓存私有数据而进一步提高了平均性能,而不管是否被修改。我们的评价表明,与最先进的可预测的一致性协议相比,迪斯科达到了7.2? - 较低的延迟界限。迪斯科也可以实现高达11.4? - (5.3? - 平均)比私人高速缓存绕过Splash-3基准。

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