DA Based FIR Filter Design Analysis using Different LUT Partitions

摘要

This paper present realization of an efficient reconfigurable distributed arithmetic (DA)-based digital finite impulse response (FIR) filter using field programmable gate array(FPGA). Usually In case of reconfigurable DA based filter Lookup tables (LUTs) are implemented using RAM. For DA computation shared-LUT concept is proposed because it is economic. In DA processing to store partial inner product result of different bit positions DA units will share the register .To implement a DA based FIR filter we are using FPGA. The proposed filter supports for maximum input sampling frequency of 442MHz and it requires less number of LUTs and Slice registers so it is area efficient design. The proposed design for different LUT partition is implemented on Xilinx vertex-5 FPGA device (XC5VSX95T-1FF1136).