机译:6-140-NW 11 Hz-8.2-KHz DVFS RISC-V微处理器使用可扩展的动态泄漏抑制逻辑
Department of Electrical and Computer Engineering University of Virginia Charlottesville VA USA;
Department of Electrical and Computer Engineering University of Virginia Charlottesville VA USA;
Department of Electrical and Computer Engineering University of Virginia Charlottesville VA USA;
Department of Electrical and Computer Engineering University of Virginia Charlottesville VA USA;
Department of Electrical Engineering and Computer Sciences University of California at Berkeley Berkeley CA USA;
Department of Electrical and Computer Engineering University of Virginia Charlottesville VA USA;
Clocks; Logic gates; Microprocessors; Voltage control; Generators; Computer architecture; Delays;
机译:动态时间片缩放可解决智能系统中主内存DVFS引起的操作系统问题
机译:Co_(68)Fe_4Cr_4Si_(13)B_(11)合金在50-10000 Hz频率范围内制成的环形磁芯的动态再磁化曲线
机译:用于实现物联网的同步逻辑和异步逻辑8051微控制器内核:动态电压缩放和变化效应的比较研究
机译:从180nm批量cmos到7 nm finfet加工的不同技术节点的动态泄漏抑制逻辑技术调查
机译:使用动态电压/频率缩放的微处理器中的身体偏置来减少电力
机译:用于多域电源管理的13-4动态电压和频率缩放(DVFS)方案