In this paper, the Cyclone series programmable logic device (FPGA) is used to implement the location detection algorithm. The implementation process requires that the storage space be occupied as small as possible, fast, and less occupied by CPU resources. High speed A/D is used for signal detection conversion. Pipeline optimization technology is adopted to improve working speed. Program module and top layer file is compiled. Experimental simulation verifies the effectiveness and real time of the algorithm.
展开▼