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1-Bit Full Adder in Perpendicular Nanomagnetic Logic using a Novel 5-Input Majority Gate

机译:使用新型5输入多数门在垂直纳米磁逻辑中的1位全加法器

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In this paper, we show that perpendicular Nanomagnetic Logic (pNML) is particularly suitable to realize threshold logic gate (TLG)-based circuits. Exemplarily, a 1-bit full adder circuit using a novel 5-input majority gate based on TLGs is experimentally demonstrated. The theory of pNML and its extension by TLGs is introduced, illustrating the great benefit of pNML. Majority gates based on coupling field superposition enable weighting each input by its geometry and distance to the output. Only 5 magnets, combined in two logic gates with a footprint of 1:95 μm2 and powered by a perpendicular clocking field, are required for operation. MFM and magneto-optical measurements demonstrate the functionality of the fabricated structure. Experimental results substantiate the feasibility and the benefits of the combination of threshold logic with pNML.
机译:在本文中,我们证明了垂直纳米磁逻辑(pNML)特别适用于实现基于阈值逻辑门(TLG)的电路。示例性地,实验证明了使用基于TLG的新型5输入多数门的1位全加法器电路。介绍了pNML的理论及其通过TLG的扩展,说明了pNML的巨大好处。基于耦合场叠加的多数门可以根据输入的几何形状和与输出的距离对每个输入进行加权。仅需要5个磁体,就可以将其集成在两个逻辑门中,占板面积为1:95μm2,并由垂直时钟场供电。 MFM和磁光测量证明了所制造结构的功能。实验结果证实了将阈值逻辑与pNML相结合的可行性和优势。

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