Implementation of UART with BIST Technique Using Low Power LFSR

摘要

Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART), mostly used for low expense, low speed, short distance data exchange between processor and peripherals. UART allows full duplex serial communication link, and is used in data communication and control system. There is a need for realizing the UART function in a single or a very few chips. Further, design systems without full testability are open to the increased possibility of product failures and missed market opportunities. Also, it is necessary to ensure the data transfer is error proof. This project targets the introduction of Built-in self test (BIST) and Status register to UART. The basic idea is to reduce the switching activity among the test patterns at the most. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The 8-bit UART with status register and BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and ISim version 14.4 and realized on FPGA.